S_B_INV=0, CLCK_WAY=0, B0DPE=0, B0ICE=0, B0MW=00, B0DCE=0, B0IPE=0, CINV_WAY=0, B0SEBE=0, CRC=000
Flash Control Register
| B0SEBE | Single Entry Buffer Enable 0 (0): Single entry buffer is disabled. 1 (1): Single entry buffer is enabled. |
| B0IPE | Instruction Prefetch Enable 0 (0): Do not prefetch in response to instruction fetches. 1 (1): Enable prefetches in response to instruction fetches. |
| B0DPE | Data Prefetch Enable 0 (0): Do not prefetch in response to data references. 1 (1): Enable prefetches in response to data references. |
| B0ICE | Instruction Cache Enable 0 (0): Do not cache instruction fetches. 1 (1): Cache instruction fetches. |
| B0DCE | Data Cache Enable 0 (0): Do not cache data references. 1 (1): Cache data references. |
| CRC | Cache Replacement Control 0 (000): LRU replacement algorithm per set across all four ways 2 (010): Independent LRU with ways [0-1] for ifetches, [2-3] for data 3 (011): Independent LRU with ways [0-2] for ifetches, [3] for data |
| B0MW | Memory Width 0 (00): 32 bits 1 (01): 64 bits |
| S_B_INV | Invalidate Prefetch Speculation Buffer 0 (0): Speculation buffer and single entry buffer are not affected. 1 (1): Invalidate (clear) speculation buffer and single entry buffer. |
| CINV_WAY | Cache Invalidate Way x 0 (0): No cache way invalidation for the corresponding cache 1 (1): Invalidate cache way for the corresponding cache: clear the tag, data, and vld bits of ways selected |
| CLCK_WAY | Cache Lock Way x 0 (0): Cache way is unlocked and may be displaced 1 (1): Cache way is locked and its contents are not displaced |
| B0RWSC | Read Wait State Control |